1. Technical Field
The present invention relates in general to a method and system for data processing and, in particular, to a method and system for allowing multiple Peripheral Component Interconnect (PCI) adapter slots on the same PCI bus to be operated simultaneously at different clock frequencies within a computer system. Still more particularly, the present invention relates to a method and system for handling multiple PCI adapter slots on the same PCI bus to be operated at bus frequencies higher than 66 MHz.
2. Description of the Related Art
A computer system typically includes several types of buses, such as a system bus, local buses, and peripheral buses. Various electronic circuit devices and components are connected with each other via these buses such that intercommunication may be possible among all of these devices and components.
In general, a central processing unit (CPU) is attached to a system bus, over which the CPU communicates directly with a system memory that is also attached to the system bus. In addition, a local bus may be used for connecting certain highly integrated peripheral components rather than a slower standard expansion bus. One such local bus is known as the Peripheral Component Interconnect (PCI) bus. Under the PCI local bus standard, peripheral components can directly connect to a PCI local bus without the need for glue logic, the "profusion of chips needed to match the signals between different integrated circuits." Thus, PCI provides a bus standard on which high-performance peripheral devices, such as graphics devices and hard disk drives, can be coupled to the CPU, thereby permitting these high-performance peripheral devices to avoid the general access latency and the bandwidth constraints that are associated with an expansion bus. An expansion bus such as an Industry Standard Architecture (ISA) bus is for connecting various peripheral devices to the computer system. These peripheral devices typically include input/output (I/O) devices such as a keyboard, floppy drives, and printers.
In accordance with the PCI local bus standard for 33 MHz operation, only four peripheral component connector slots may be attached to a PCI bus due to loading constraints on the bus. Similarly, under the PCI local bus standard for 66 MHz operation, only two peripheral component connector slots may be attached to a PCI bus. In order to overcome this technical constraint, designers may add a second or more PCI local buses that give the end user of a computer system the advantage of adding on more slots per bus. However, a PCI host bridge is required for transferring information from the PCI bus to the system bus. Therefore, with the addition of more than one PCI local buses, designers have had to add on multiple PCI host bridges and/or PCI-to-PCI bridges for supporting the multiple PCI buses, thereby increasing the cost and complexity of the system.
The PCI local bus standard is defined to be processor independent, thereby enabling efficient transition to future processor generations having different clock frequencies. Processor independence has the added advantage of allowing the PCI local bus to be optimized for I/O functions, enabling concurrent operation of the local bus with the processor/memory subsystem, and accommodating multiple high performance peripherals. To accommodate these high performance peripherals, the current PCI local bus standard calls out for 66 MHz bus operation having forward and backward compatibility (doubling the bandwidth capabilities of the current 33 MHz definition.) However, there is a limitation in that a 66 MHz PCI device operates as a 33 MHz PCI device when it is connected to a 33 MHz PCI bus. To overcome this technical constraint, designers in the past have added a second PCI local bus having its own independent clock frequency, thereby allowing the end user to take advantage of adding in 66 MHz PCI devices. Additionally, it is envisioned that there will be a movement to enhance video and multimedia displays (i.e., HDTV and 3-D graphics) and other high bandwidth I/O, which will increase the local bus bandwidth requirements beyond 66 MHz.
Therefore, it is desirable in a PCI-based system requiring multiple PCI host bridges and/or PCI-to-PCI bridges supporting multiple PCI buses, that a single PCI host bridge support the multiple PCI buses thus minimizing the number of required bridges. Furthermore, it is desirable to have a single PCI host bridge that supports both 33 MHz and 66 MHz bus operation having more PCI peripheral component slots on a PCI bus than is defined by the PCI local bus standard. Lastly, it is desirable to allow different PCI devices on the same or different PCI buses to be operated at different frequencies, including bus frequencies higher than 66 MHz, while still maintaining backward compatibility as defined by the current PCI bus architecture. The subject invention herein solves all of these problems in a new and unique manner which has not been part of the art previously.